A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks

Various types of Networks-on-Chips (NoCs) have been employed light-weight routers compared with those in parallel computers, and a virtual-channel mechanism, which requires additional logic and pipeline stages, is one of the crucial factors for a low cost implementation of an NoC router in the case of simple tile-based architectures. Although a torus network, which exploits wrap-around channels, achieves higher throughput and lower latency than a same-sized mesh, a virtual-channel mechanism is usually required to avoid deadlocks in tori with dimension-order routing. In this paper, we propose a scheme to remove virtual channels in tori by accomplishing the following steps: 1) providing a mechanism which allows wraparound channels to be individually disabled in each router, 2) a task mapping strategy that carefully assigns tasks to a tori, so that as many wrap-around channels as possible are exploited without introducing deadlocks or performance degradation. Additionally, we extend this strategy to avoid deadlocks when application traffic patterns are unknown or incompletely analyzed. Although the proposed mapping does not use virtual channels, it achieves almost the same performance as conventional mapping in tori in ten traces. Moreover, the hardware amount of the proposed router can be decreased to 52.4% of a conventional router providing two virtual channels for tori.